1. Field of the Invention
The present invention pertains to thin film capacitors, more particularly to thin film capacitors formed on metal foil that are embedded into printed wiring boards (PWB) and provide capacitance for decoupling and controlling voltage for integrated circuit die that are mounted on the printed wiring board.
2. Description of Related Art
Semiconductor devices including integrated circuits (IC) are operating at increasingly higher frequencies, higher data rates and lower voltages. This means that noise in the power and ground (return) lines and the need to supply sufficient current to accommodate faster circuit switching require lower impedance in the power distribution system. To lower noise and stabilize power to the IC, impedance in conventional circuits is reduced by the use of additional surface mount technology (SMT) capacitors interconnected in parallel. The use of higher operating frequencies, that is, higher IC switching speeds, demands that voltage response times to the IC be faster. The use of lower operating voltages requires voltage variations (ripple) and noise has to be lower.
For example, as a microprocessor IC switches and begins an operation, it calls for power to support the switching circuits. If the response time of the voltage supply is too slow, the microprocessor will experience a voltage drop or power droop that will exceed the allowable ripple voltage and noise margin and the IC will trigger false gates. Additionally, as the IC powers up, a slow response time will result in power overshoot. Power droop and overshoot must be controlled within allowable limits by the use of capacitors that are close enough to the IC that they provide or absorb power within an appropriate response time.
Conventional designs for printed wiring boards (PWBs) generally place capacitors for decoupling and dampening power droop or overshoot as close to the IC as possible to improve capacitor performance. In these designs, capacitors are surface mounted on the PWB and a large number of them requires complex electrical routing which leads to inductance. As frequencies increase and operating voltages continue to drop, power increases and higher capacitance has to be supplied at increasingly lower inductance levels. A solution would be to incorporate a high capacitance density, thin film ceramic capacitor in the PWB package onto which the IC is mounted. A single layer ceramic capacitor directly under the IC reduces inductance to a minimum and the high capacitance density provides the capacitance to satisfy the IC requirements. Such a high capacitance density capacitor in the PWB can provide current at a significantly quicker response time and lower inductance.
In achieving a high capacitance density capacitor, there are several considerations. One is to choose a thin film capacitor dielectric. Thin film capacitor dielectrics having a thickness of less than 1 micron (μm) are known.
Another consideration is to choose a capacitor dielectric having a high permittivity or dielectric constant [“Dk”]. Thin film capacitor dielectrics having high dielectric constants are well known, especially in ferroelectric ceramics. Ferroelectric materials with high dielectric constants include perovskites of the general formula ABO3 in which the A site and B site can be occupied by one or more different metals. For example, a high dielectric constant is realized in crystalline barium titanate (BT), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), lead magnesium niobate (PMN) and barium strontium titanate (BST) and these materials are commonly used in surface mount component devices. Barium titanate based compositions are particularly useful not only because have high dielectric constants and are lead free.
Deposition of thin films onto a substrate is done by, for example, sputtering, laser ablation, chemical vapor deposition, and chemical solution deposition and initially results in either an amorphous or a partially crystalline film, depending upon deposition conditions. Amorphous compositions have low Dk (approximately 20) and have to be annealed at high temperatures to induce crystallization and the desired high Dk phase. High temperature annealing of barium titanate thin films formed on base metal foils, such as copper or nickel, require low oxygen partial pressures to avoid oxidation of the metal.
The high Dk phase in barium titanate based dielectrics can be achieved only when grain size exceeds approximately 0.1 micron, which means annealing at temperatures as high as 900° C. or higher may be required to develop the appropriate grain size. U.S. Pat. No. 7,029,971 to Borland et al. considers these dielectric compositions and annealing temperatures in developing capacitors with capacitance densities greater than 0.5 micro-Farad per square centimeter (μF/cm2).
A further consideration in achieving a high capacitance density capacitor is the manner of formation of the top electrode of the capacitor. Typically, after annealing the dielectric at high temperature, depositing an electrode onto the dielectric by sputtering or other similar techniques can result in thin electrodes smaller than 0.1 micron. However, making thin electrodes typically requires a very long sputtering time and is therefore time consuming and expensive. It also exposes the dielectric to plating solutions that can compromise dielectric reliability. A more economical method for forming the top electrode of the capacitor is needed. Thus, the problem to be solved is to make a usable high capacitance density capacitor formed on foil and having a top electrode between 1 and 30 microns, that is, a thick top electrode. This consideration is not suggested, hinted at nor is a predictable result of U.S. Pat. No. 7,029,971 to Borland et al.